Integrated circuit design in the deep-submicron process nodes (e.g., 32 nm and beyond) involves a number of non-trivial challenges, and particular complications have been faced with respect to integration of highly porous dielectric materials. Continued process scaling will tend to exacerbate such problems.
These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines, right angles, etc., and some features may have surface topography or otherwise be non-smooth, given real world limitations of fabrication processes. In short, the figures are provided merely to show example structures.